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hardEmbedded Systems Engineer interview question

How do you safely share data between interrupt handlers and tasks while keeping interrupt latency low?

What the interviewer wants to hear

  • Keep ISRs short and defer work to tasks
  • Use RTOS FromISR queues or task notifications
  • Lock-free single-producer single-consumer ring buffers
  • Short critical sections only when needed, measured
  • Understand atomicity, volatile and memory barriers
  • Respect the RTOS max syscall interrupt priority

Model answer

My rule is that ISRs capture data and signal, and tasks do the processing. For low rates I use RTOS queues or task notifications with the FromISR APIs and yield if a higher-priority task woke. For streams like UART or ADC data, I use a single-producer single-consumer ring buffer: only the ISR writes the head, only the task writes the tail, and indices are aligned 32-bit values, so no locks are needed on a single core. Data is written before the index is published, with volatile and barriers where reordering is possible. When a multi-word structure must be updated together, I use a very short critical section, or BASEPRI masking that leaves the highest-priority interrupts running, and I measure how long interrupts are disabled. I also make sure ISRs that call the kernel are at or below the RTOS max syscall priority.

Can you answer it under time pressure?

Take a timed hard round and get scored on every answer.

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