hard20 pts · first answer countsembedded-cconcurrency

Flag cleared as the last ISR line

On a Cortex-M4, a timer ISR clears the peripheral flag as its very last instruction. The ISR sometimes runs a second time for one event. Why?

A.The NVIC always runs each ISR twice by designB.The flag write is still in flight on the bus when the ISR exitsC.Clearing flags must be done before entering the ISRD.The timer counts twice as fast inside an ISR

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Flag cleared as the last ISR line

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